1. Field of the Invention
The present invention relates to an inexpensive process for producing a multiplicity of semiconductor wafers with a local flatness, expressed as the SFQRmax value for a surface grid of 25 mmxc3x9725 mm, of less than or equal to 0.13 xcexcm. Semiconductor wafers with a high flatness of this nature are suitable for use in the semiconductor industry, in particular for the fabrication of electronic components with line widths of less than or equal to 0.13 xcexcm.
2. The Prior Art
A semiconductor wafer which is to be suitable in particular for the fabrication of electronic components with line widths of less than or equal to 0.13 xcexcm must have a high local flatness in all partial areas. A suitable measure of flatness which takes into account the focussing capabilities of a stepper, is the SFQR (site front-surface referenced least squaresxe2x88x92range=range of the positive and negative deviation from a front surface defined by minimizing the mean square error for a component area of defined size). The parameter SFQRmax specifies the maximum SFQR value for all the component areas on a semiconductor wafer. A generally accepted rule of thumb states that the SFQRmax value of a semiconductor wafer must be less than or equal to the possible line width on this wafer for semiconductor components that are to be produced on it. If this value is exceeded, the stepper experiences focussing problems and the component in question is thus lost.
The final flatness of a semiconductor wafer is generally produced by a polishing process. In order to improve the flatness values of a semiconductor wafer, apparatuses and processes for the simultaneous polishing of front and back sides of the semiconductor wafer have been provided and developed further. This so-called double-side polishing is described for example in U.S. Pat. No. 3,691,694. In accordance with an embodiment of double-side polishing which is described in EP 208 315 B1, semiconductor wafers in carriers which are made of metal or a plastics material and have suitably dimensioned cutouts are moved along a path. This path is predetermined by the machine and process parameters between two rotating polishing plates, which are covered with a polishing cloth, in the presence of a polishing fluid, and hence polished.
It is known to integrate double-side polishing into process sequences for producing semiconductor wafers. EP 754 785 A1 describes the sequence of sawing a semiconductor crystal, followed by edge rounding, double-side polishing and final polishing of the semiconductor wafers obtained. In EP 755 751 A1, it is proposed to employ a double-side grinding process between the edge rounding and double-side polishing. EP 798 405 A2 describes the sequence of sawingxe2x80x94edge roundingxe2x80x94grindingxe2x80x94alkaline etchingxe2x80x94double-side polishing. The preferred embodiments of U.S. Pat. No. 5,756,399 include the process sequence of sawingxe2x80x94grindingxe2x80x94alkaline etchingxe2x80x94edge roundingxe2x80x94double-side polishing. U.S. Pat. No. 5,899,743 describes the sequence of steps of sawingxe2x80x94edge roundingxe2x80x94lappingxe2x80x94double-side polishingxe2x80x94edge polishingxe2x80x94final polishing. DE 198 33 257 C1 discloses the process sequence of sawingxe2x80x94edge roundingxe2x80x94grinding xe2x80x94etchingxe2x80x94double-side polishingxe2x80x94final polishing, the etching in this case being carried out using an improved acid etching process. A common feature of these process sequences is that after the double-side polishing they lead to a semiconductor wafer with SFQRmax values of greater than 0.13 xcexcm.
The production of a semiconductor wafer with SFQRmax values of less than or equal to 0.13 um is described in EP 961 314 A1 which describes the use of expensive plasma etching processes. This production also forms the subject of DE 199 05 737 A1. This discloses an improved double-side polishing process by maintaining tightly restricted thickness ratios between carrier thickness and thickness of the semiconductor wafer after the polishing process. This application specifies that preferably from 10 xcexcm to 60 xcexcm, and particularly preferably 20 xcexcm to 50 xcexcm, of material are removed in the case of the polishing of silicon wafers. A common feature of both processes is that a percentage of wafers produced in this way do not satisfy the quality features stipulated for further processing, such as a surface which is free from flaws in terms of scratches, stains and light point defects. This percentage always occurs in practical operation, and thus has to be discarded, which has an adverse effect on the production costs for wafers of this nature.
Therefore, it is an object of the present invention to provide a process for producing a multiplicity of semiconductor wafers with an SFQRmax value of less than or equal to 0.13 xcexcm which is superior to the known processes of the prior art in terms of the production costs. Furthermore, it was intended that the further properties of the semiconductor wafers produced using this process should be at least as good as those of semiconductor wafers produced according to the prior art.
This object is achieved according to the present invention by providing a process for producing a multiplicity of semiconductor wafers, which comprises the following individual steps:
(a) simultaneously polishing a front side and a back side of each semiconductor wafer between rotating polishing plates with a polishing fluid being supplied, the semiconductor wafer in each case resting in a cutout in a carrier and being kept on a specific geometric path, and all semiconductor wafers having a thickness t1 following the polishing;
(b) assessment of each semiconductor wafer with regard to quality features which are stipulated for further processing;
(c) further simultaneously polishing a front side and a back side of each of those semiconductor wafers which, according to quality inspection (b), do not satisfy the stipulated quality features, these semiconductor wafers having a thickness t2 following the further polishing; and
(d) further assessment of each of those semiconductor wafers which were fed to step (c) with regard to quality features stipulated for further processing.
An essential feature of the invention is that those semiconductor wafers from a multiplicity of double-side polished semiconductor wafers which do not satisfy the quality features specified for further processing can be fed to a further double-side polishing step. Thus there will be an increasing of the overall yield and therefore a reduction in production costs. Also the reduction in thickness can be selected to be sufficiently small for it to be possible to maintain the standard tolerances for the wafer thickness which are required in semiconductor fabrication. In the description which follows, double-side polishing in which only a relatively small reduction in thickness is desired is referred to as flash DSP. The fact that a flash DSP process of this nature allows flawed semiconductor wafers to be machined with a high yield without having an adverse effect on the local geometry values was unexpectedly surprising and not predictable.
The starting product for the process is a multiplicity of semiconductor wafers which have been cut from a crystal in a known way. For example these wafers are from a single silicon crystal which has been cut to length and cylindrically ground, have had their edges rounded by means of a suitably profiled grinding wheel or a plurality of different grinding wheels of this nature and whose front and/or back sides have if appropriate been treated by means of grinding, lapping and/or etching processes. If desired, the crystal may be provided with one or more orientation features in order to identify the crystal axes, for example with a notch and/or a flat. Furthermore, it is possible for the edge of the semiconductor wafers to be polished before the process according to the invention is carried out.
The end product of the process is a multiplicity of double-side polished semiconductor wafers which satisfy the demands imposed on semiconductor wafers to be used as starting material for semiconductor component processes with line widths of less than or equal to 0.13 xcexcm. The inventive wafers are superior to the semiconductor wafers produced according to the prior art in terms of their production costs on account of high yields and/or reduced levels of material abrasion.
The process according to the invention may in principle be used to produce a multiplicity of wafer-like bodies which consist of a material which can be machined using the chemical mechanical double-side polishing process employed. Examples of such materials include silicon, silicon/germanium and so-called III-V semiconductors, such as gallium arsenide. The process is particularly suitable for the production of single crystal silicon wafers with diameters of in particular 200 mm, 300 mm, 400 mm and 450 mm and thicknesses from a few 100 xcexcm to a few cm, preferably from 400 xcexcm to 1200 xcexcm. The semiconductor wafers may either be used immediately as starting material for the production of semiconductor components or may be supplied for their intended purpose after a final polishing step according to the prior art has been carried out and/or after layers, such as back-side seals or an epitaxial coating on the wafer front side, for example with silicon, have been applied and/or after a heat treatment, for example under a hydrogen or argon atmosphere. In addition to the production of wafers from a homogenous material, the invention may, of course, also be used to produce semiconductor substrates with a multilayer structure, such as SOI wafers (silicon-on insulator wafers).
The process is described further on the basis of the example of the production of a multiplicity of silicon wafers.
In principle, it is possible for a multiplicity of silicon wafers which have been sawn, for example by an annular sawing or wire sawing method and whose areas close to the surface, depending on the diameter and the type of sawing process, have a damaged crystalline structure down to a depth in the range of 10 to 40 xcexcm, to be subjected directly to the novel process sequence of double-side polishing (a), quality assessment (b), flash DSP polishing of the reject wafers (c), and further quality assessment of the wafers (d) polished in (c). However, it is sensible, and therefore preferable, for the sharply delimited, and therefore very mechanically sensitive, edges of the wafers to be rounded with the aid of suitably profiled grinding wheels. Suitable grinding wheels consist of metal-bonded diamonds or resin-bonded diamonds. To provide an edge with little damage while reducing the machining times and therefore the costs of the edge-rounding step, it is customary according to the prior art, and therefore preferable within the context of the invention, to use a two-stage process firstly involving a grinding wheel with a relatively coarse diamond grain. This is followed by a grinding wheel with diamonds of a relatively fine grain. In the first step, it is particularly preferable to employ a metal-bonded grinding wheel with diamonds with a 400 mesh grain (grain size range 30-50 xcexcm) to 600 mesh (grain size range 20-30 xcexcm). In the second step it is particularly preferable to use a grinding wheel of similar structure with diamonds with a grain of 1000 mesh (grain size range 8-15 xcexcm) to 1500 mesh (grain size range 5-10 xcexcm) in case the further process sequence also involves an etching step with the removal of destroyed crystal layers being carried out from the edge of the wafer.
In the examples which follow later in the description, this procedure is referred to as xe2x80x9ccoarse edge roundingxe2x80x9d. If there is no etching step in the further process sequence, it is particularly preferable to use a two-stage process for edge rounding in which in the first step a metal-bonded grinding wheel with diamonds with a grain of 400 mesh (grain size range 30-50 xcexcm) to 600 mesh (grain size range 20-30 xcexcm) is used. In the second step a resin-bonded grinding wheel with diamonds with a grain of 1200 mesh (grain size range 7-12 xcexcm) to 2000 mesh (grain size range 4-6 xcexcm) is used. In the examples which follow later in the description, this procedure is referred to as xe2x80x9cfine edge roundingxe2x80x9d. Alternative techniques for fine edge rounding which have by now become established on the market, for example the combination of conventional edge rounding with a mechanical polishing part, are also suitable if there is no etching step carried out.
To improve the geometry and abrade some of the disrupted crystal layers, it is possible for the silicon wafer to be subjected to a mechanical abrasion step, such as lapping or grinding, in order to reduce the amount of material which has to be removed in the double-side polishing step (a). It is preferable for the silicon wafer to be subjected to a surface grinding step, in which either one side is ground or both sides are ground sequentially or both sides are ground simultaneously. Sequential surface grinding of the front and back sides of the wafers is particularly preferred. To remove the damage to the wafer surface and edge which inevitably results from the mechanical process steps and to remove any impurities which are present, for example metallic impurities bonded in the damage, it is possible for an etching step to follow at this point. This etching step may be carried out either as a wet chemical treatment of the silicon wafer in an alkaline or acid etching mixture or as a plasma treatment. An acid etching step in a mixture of concentrated aqueous nitric acid and concentrated aqueous hydrofluoric acid in accordance with the embodiment claimed in DE 198 33 257 C1 is preferred.
A preferred starting material for the process according to the invention is a multiplicity of semiconductor wafers made from silicon, produced by sawing of a single silicon crystal, followed by fine edge rounding. Another preferred starting material is a multiplicity of semiconductor wafers made from silicon produced by sawing of a single silicon crystal followed by fine edge rounding and sequential surface grinding. Another preferred starting material is a multiplicity of semiconductor wafers made from silicon, produced by sawing of a single silicon crystal followed by coarse edge rounding and wet chemical etching. A particularly preferred starting material is a multiplicity of semiconductor wafers made from silicon with a diameter of greater than or equal to 200 mm, produced by wire sawing of a single silicon crystal, followed by coarse edge rounding, sequential surface grinding of both sides of the wafers, so that from 10 xcexcm to 100 xcexcm of silicon is abraded on each side, and wet chemical etching in an acid etching mixture with from 5 xcexcm to 50 xcexcm of silicon being removed from each side of the wafers.
Steps (a) to (d) of the invention for inexpensively converting the starting material into a multiplicity of double-side polished silicon wafers which satisfy the demands imposed on semiconductor wafers to be used as starting material for semiconductor component processes with line widths of less than or equal to 0.13 xcexcm are described in more detail below.
Double-side polishing step (a)
A commercially available double-side polishing machine of suitable size can be used to carry out the polishing step (a) according to the invention. For cost reasons it is sensible to polish a multiplicity of silicon wafers simultaneously. The polishing machine substantially comprises a bottom polishing plate which can rotate freely in the horizontal direction and a top polishing plate which can rotate freely in the horizontal direction. Both of these plates are covered with in each case one polishing cloth, and the machine allows semiconductor wafers, in this case silicon wafers, to be polished so that material is abraded on both sides, with a polishing fluid of suitable chemical composition being supplied continuously. It is particularly preferable for the polishing to use a commercially available polyurethane polishing cloth with a hardness of 60 to 90 (Shore A), with continuous supply of a polishing fluid with a pH of from 10 to 11, comprising 1 to 5% by weight SiO2 in water, under a polishing pressure of from 0.1 to 0.3 bar.
The silicon wafers are held on a geometric path which is defined by machine and process parameters by carriers which have cutouts of sufficient dimensions to hold the silicon wafers. The carriers are in contact with the polishing machine, for example by means of a pin gearing or involute toothing, via a rotating inner pinned or toothed ring and an outer pinned or toothed ring which generally rotates in the opposite direction. As a result the carriers are set in rotating motion between the two polishing plates. In principle, the carriers may be made, for example, from metal, plastics, fiber-reinforced plastics or plastic-coated metal. Carriers made from steel or from fiber-reinforced plastics are preferable. On account of their high dimensional accuracy and chemical stability, carriers made from stainless chromium steel are particularly preferable. To prevent the edge of the wafers from being damaged by the inner edge of the cutout in the carrier during polishing, it is sensible and therefore preferable for the inside of the cutout to be lined with a plastic coating of the same thickness as the carrier, as described in EP 208 315 B1. Suitable plastics are in this case, for example, polyamide, polyethylene, polypropylene, polyvinyl chloride, polytetrafluoroethylene or polyvinylidene difluoride, which are all equally preferable.
The carriers for the step (a) according to the invention have a preferred thickness t1L of from 400 to 1200 xcexcm. In order to have silicon wafers with a high local flatness after step (a), it is particularly preferable to use a double-side polishing process in which the selected thickness of the carriers t1L is close to the desired final thickness t1 of the silicon wafers after step (a). This desired final thickness ultimately is dependent on the diameter of the silicon wafers and on the planned application. A polishing process of this nature is described in DE 199 05 737 A1. A characteristic feature of this design variant is that the starting thickness t0 of the silicon wafers to be polished is particularly preferably 30 to 70 xcexcm greater than the carrier thickness t1L, and the final thickness of the polished wafers t1 is particularly preferably 5 to 15 mm greater than the carrier thickness t1L. It is particularly preferable for the amount of silicon removed t0xe2x88x92t1 to be between 20 xcexcm and 50 xcexcm.
Within the context of the comments made with regard to these particularly preferred thickness ratios, the polishing time required to achieve a predetermined removal of silicon is of considerable importance. The polishing time (in min) is determined by dividing the difference between the starting thickness t0 (in xcexcm) and the target thickness t1 (in xcexcm) of the silicon wafers by the stock removal rate of the polishing machine (in xcexcm/min). The permissible target thickness t1 is determined by the specification window stipulated by the further processor of the wafers, usually target thickness tTxc2x115 xcexcm or tTxc2x125 xcexcm, and the current thickness t1L of the carriers used, the difference t1xe2x88x92t1L particularly preferably being between 5 xcexcm and 15 xcexcm. The carriers made from stainless chromium steel which are particularly preferable to use can be produced with a very accurate thickness, for example by employing lapping or grinding processes. However, if the particularly preferred polishing parameters are selected, the carriers become slightly, although homogeneously, worn during prolonged operating periods. To determine the polishing times as accurately as possible, therefore, the carrier thickness t1L should be determined periodically, for example with the aid of calipers or a micrometer screw. If the thickness of the carriers t1L, as a result of a certain period of use, has fallen below a defined action limit, for example tTxe2x88x9210 xcexcm or tTxe2x88x9215 xcexcm, these carriers can be used without problems to carry out step (c), which is described further below, of the process sequence according to the invention.
After the end of polishing (a), if appropriate adhering polishing fluid is cleaned off the silicon wafers and the wafers are dried.
Assessment step (b)
There follows an assessment of the multiplicity of silicon wafers with regard to quality features which are influenced by the double-side polishing step (a) and have been specified by the further processor of the wafers, using methods which are known to the person skilled in the art. Features of this nature may, for example, be local geometry data and wafer thickness t1. These data are determined using a commercially available measuring instrument which operates on a capacitive or optical principle. The data are advantageously electronically stored in a database and are available for the statistical process control (SPC) which is desirable in production mode. It is also possible and advantageous to produce a data technology link between measuring instrument and polishing machine via a master computer. In this way it is possible, for example during consecutive polishing runs with wafer material of the same type, by specifying starting thickness t0 and target thickness t1, to automatically predetermine the polishing time for the subsequent polishing run by calculating the current abrasion rate.
Other quality features assessed in step (b) may include properties which affect the front side, the back side, and/or the edge of the wafers. In this context, it is very important to assess the occurrence and extent of scratches, stains, light point defects and other deviations from the ideal silicon surface, such as for example damage caused by prior mechanical processes which has not been eliminated by polishing. An assessment of this nature is in practice usually carried out visually by trained personnel under strongly focused light, so-called haze light. Alternatively, or in addition, it is also possible for the wafers to be assessed using technical accessories, such as for example a microscope or a laser detection unit.
Those silicon wafers from the multiplicity of silicon wafers assessed which satisfy the quality demands imposed are temporarily stored, for example in a stocker as described in EP 866 497 A2, or are fed directly for their further intended use. Those silicon wafers from the multiplicity of silicon wafers assessed which do not satisfy the quality demands imposed are separated out and in one embodiment are fed directly for further machining in accordance with step (c). However, they may also be collected for a certain period and then fed to step (c).
Flash DSP step (c)
The silicon wafers of thickness t1 which have been separated out in step (b) are now fed to a further double-side polishing step. This step leads to wafers of a thickness t2 and, with particularly preferred amounts of removed silicon t1xe2x88x92t2 of between 2 xcexcm and 10 xcexcm, removes considerably less material than step (a). Step (a) particularly preferably involves amounts of removed silicon t0xe2x88x92t1 of between 20 xcexcm and 50 xcexcm. Therefore, step (c), unlike the double-side polishing step (a), can be referred to as a flash DSP process. The basic execution of step (c) can take place without problems as described under step (a). The carrier thickness t2L of the carriers used in step (c) may be considerably less, for example 20 xcexcm to 200 xcexcm less, than the starting thickness of the wafers t1. However, with a view to achieving optimum local geometry results, it has proven advantageous for the flash DSP to involve the use of carriers within a defined thickness window in which the thickness difference t1xe2x88x92t2L is between 5 xcexcm and 30 xcexcm. Also the thickness difference t2xe2x88x92t2L is between 2 xcexcm and 10 xcexcm; this procedure is therefore particularly preferable.
With regard to the size of double-side polishing machine, there are in principle no restrictions for the flash DSP process (c). Step (c) may be carried out either on the same polishing machine as step (a) or on a polishing machine of the same design or on a polishing machine which simultaneously double-side polishes more or fewer semiconductor wafers than that used for step (a). In view of the object of the invention to provide a process for producing a multiplicity of semiconductor wafers which is improved in terms of the production costs, it may be sensible to use a polishing machine for machining single wafers or for machining only a few wafers, for example 3 to 5 wafers, per polishing run. However, it is equally possible without problems, and even, under certain circumstances, advantageous in terms of costs, to use a polishing machine which allows the simultaneous polishing of a larger number of wafers, for example from 15 to 30 wafers. If the total number of wafers provided for flash DSP is not a multiple of the number of wafers which would completely occupy the machine, the number of carriers used can be reduced accordingly. However, it is more sensible, with a view to optimizing the running of a double-side polishing machine of this type, and therefore preferable, for the corresponding polishing run to be filled up. Thus the carriers are fully occupied, with further similar wafers that are of the starting thickness t1 but are not included in the multiplicity of semiconductor wafers, i.e. with so-called dummy wafers.
After the end of the flash DSP process (c), adhering polishing fluid is once again cleaned off the silicon wafers and the wafers are dried.
Assessment step (d)
After they have passed through step (c), the wafers involved are fed for further assessment in accordance with step (b). In this assessment, it is found that, depending on the gravity of the flaws which lead to the flash DSP step being carried out, on average between 70% and 95% of the wafers now satisfy the quality criteria demanded. This produces the result that the total yield of the process sequence (a)-(b)-(c)-(d) according to the invention is significantly increased. For example, it was found that silicon wafers which according to geometry measurement carried out in step (b) had local flatness values SFQRmax of less than or equal to 0.13 xcexcm still satisfy this criterion. On the other hand, a high percentage of wafers which were produced by a shortened process sequence, for example sawingxe2x80x94edge roundingxe2x80x94double-side polishing step (a) or sawingxe2x80x94edge roundingxe2x80x94etchingxe2x80x94double-side polishing step (a) and were separated out during the geometry measurement, now satisfy the required quality of SFQRmax less than or equal to 0.13 xcexcm. Equally, many wafers which did not successfully pass step (b) on account of scratches, stains, light point defects and further surface flaws, now satisfy the demands imposed in order for them to be processed further. As a result of the particularly preferred amounts of silicon removed t1xe2x88x92t2 in step (c) of between 2 xcexcm and 10 xcexcm, the thickness of the wafers fed to steps (c) and (d) differs from the wafers which have been temporarily stored or passed onwards after steps (a) and (b) only by this amount. Step (c) is carried out in such a manner that t2 lies within the thickness window which is intended for further use. Depending on the particular requirements, the wafers which have passed through steps (a) to (d) can be combined with those wafers which have only passed through steps (a) and (b) in batches or in a manner appropriate for the wafers, to form a multiplicity of semiconductor wafers according to the invention.
Depending on their intended further purpose, it may be necessary for the front side of each of the multiplicity of silicon wafers produced using the process according to the invention to undergo final polishing in accordance with the prior art, for example using a soft polishing cloth with the aid of an alkaline polishing fluid based on SiO2. To obtain the very low, uniformly distributed local geometry values, the amount of silicon abraded from each wafer in this step should be relatively small, lying, for example, between 0.1 and 0.7 xcexcm.
If necessary, a heat treatment of the multiplicity of semiconductor wafers can be introduced at any desired point in the process sequence. For example neat treatment is useful in order to eliminate thermal donors, to anneal out any disturbance in crystal layers close to the surface, or to bring about controlled reduction of the dopant levels in the aforementioned layers. Furthermore, laser writing in order to identify the wafers and/or an edge polishing step may be inserted at any suitable point in the process sequence, for example before or after grinding in the case of the laser marking, and before, during or after the double-side polishing step (a) in the case of the edge polishing. A series of further process steps which are required for certain products, such as for example the application of back side coatings of polysilicon, silicon dioxide or silicon nitride, or the application of an epitaxial layer of silicon or other semiconducting materials to the front side of the silicon wafers can also be included at suitable points in the process sequence using processes which are known to the person skilled in the art. Furthermore, it may also be desirable for the semiconductor wafers to undergo batch or individual wafer cleaning according to the prior art before or after individual process steps.
Semiconductor wafers, in particular silicon wafers, produced according to the invention fulfill the demands imposed on the production of semiconductor components with line widths of less than or equal to 0.13 xcexcm. The process according to the invention has proven to be an optimum solution for reducing the production costs of silicon wafers having the features which have been outlined. It is surprising and unexpected that machining double-side polished wafers which do not satisfy the quality features stipulated for further processing, such as the extent of scratches, stains and light point defects, by means of a flash DSP process with only from 2 xcexcm to 10 xcexcm of material being removed is successful in high yields without the local flatness of the wafers being adversely affected. In fact, the opposite is the case: the positive influence of the flash DSP step (c) on the local geometry values means that it is even possible to impose lower geometry demands on the starting product or on the product of the double-side polishing step (a) in the sequence according to the invention. This opens up the possibility of further decrease in the production costs by reducing the amount of material abraded or eliminating process steps such as grinding or etching.